1. Field of the Invention
The present invention relates to a level converting circuit for converting a level of an input signal, an internal potential generating circuit for generating an internal potential, an internal potential generating unit for generating an internal potential, a semiconductor device and method of manufacturing a transistor. More specifically, it relates to a level converting circuit capable of preventing through current, an internal potential generating circuit providing higher efficiency in generating internal potential, an internal potential generating unit facilitating setting of performance, a highly reliable semiconductor device and to a method of manufacturing a transistor having high breakdown voltage.
2. Description of the Background Art
Conventional level converting circuits are disclosed, for example, in Japanese Patent Laying-Open Nos. 4-223713, 4-269011 and 2-37823.
FIG. 75 is a schematic diagram showing a conventional level converting circuit.
Referring to FIG. 75, the conventional level converting circuit includes PMOS transistors 3 and 9, NMOS transistors 5 and 13, and an inverter 17. PMOS transistor 3 and NMOS transistor 5 are connected in series between a ground node and a node having boosted potential Vpp.
PMOS transistor 9 and NMOS transistor 13 are connected in series between the ground node and the node having boosted potential Vpp. PMOS transistor 3 has its gate connected to the drain of NMOS transistor 13. PMOS transistor 9 has its gate connected to the drain of NMOS transistor 5.
A signal IN is input to the gate of NMOS transistor 5. A signal IN inverted by inverter 17 is input to the gate of NMOS transistor 13. A node between PMOS transistor 9 and NMOS transistor 13 is an output node, and a level converted signal OUT is output therefrom.
The operation will be described. The signal IN is a clock signal setting power supply potential Vcc and ground potential GND to "H" (high) level and "L" (low) level, respectively. When the signal IN is at the "H" level, NMOS transistor 5 and PMOS transistor 9 turn on. Thus, the signal OUT having the level of the boosted potential Vpp is output. More specifically, the signal IN having the level of power supply potential Vcc is converted to be the signal OUT having the higher level, that is, the level of the boosted potential Vpp.
When the signal IN is at the "L" level, PMOS transistor 3 and NMOS transistor 13 turn on. Therefore, the signal OUT having the level of the ground potential is output.
However, in the conventional level converting circuits, sometimes PMOS transistor 3 and NMOS transistor 5 or PMOS transistor 9 and NMOS transistor 13 may simultaneously be turned on. When the signal IN is at "L" level, NMOS transistor 5 and PMOS transistor 9 are off. If the signal IN attains to the "H" level next, it is possible that PMOS transistor 9 and NMOS transistor 5 turn on before PMOS transistor 3 and NMOS transistor 13 turn off.
When the signal IN is at the "H" level, PMOS transistor 3 and NMOS transistor 13 are off. It is possible that PMOS transistor 3 and NMOS transistor 13 turn on before PMOS transistor 9 and NMOS transistor 5 turn off, when the next "L" level signal IN is input.
From the foregoing, the conventional level converting circuit experiences the problem that through current flows from the node having boosted potential Vpp to the ground node.